The present invention relates to a method of forming a connection hole, which is applied to the field of a fine device processing in manufacture of semiconductor devices and the like, and particularly to a method of easily ensuring a sufficient etching selection ratio in a self-aligned contact process using an etching stopper film.
In a manufacturing process for semiconductor devices to which a design rule since the level of 0.3 .mu.m is applied, there occurs a problem that a design size (=hole diameter+design allowance) of a connection hole becomes excessively large when the design allowance of the connection hole is determined in consideration of a variation in alignment with a lower interconnection. The variation in alignment is due to shortage of an aligning performance of a reduction profile exposure system used for lithography. Such a variation is a factor particularly difficult in scale-down among various scaling factors included in semiconductor manufacturing processes, and it is often regarded as the factor exerting an effect on the limitation of the exposure technique more than the resolution.
In view of the foregoing, various kinds of self-aligned contact (SAC) processes capable of eliminating a design allowance for alignment on a photomask have been proposed. In particular, a process using a silicon nitride (SiN) film as an etching stopper film has been mostly examined in terms of an advantage in that an additional exposure process is not required.
This process will be described with reference to FIG. 11.
FIG. 11 shows a state in which a contact hole for bringing an upper interconnection (bit line) in contact with a substrate between adjacent gate electrodes (word lines) is partially opened in an SRAM memory. The steps until the state shown in FIG. 11 is obtained will be briefly described. Gate electrodes 83 (poly Si/WSix) are formed through a thermal oxidized gate oxide film 82 (SiO.sub.2) on the surface of a silicon substrate 81 (Si) previously processed in well formation and element isolation. An upper surface and side surfaces of each gate electrode 83 are respectively covered with an offset oxide film 84 (SiOx) and a side wall 85 (SiOx). Source/drain regions 86 having an LDD structure are formed in surface layer portions of the silicon substrate 81 in self-alignment with the gate electrode 83 and the side wall 85.
A SiN etching stopper film 87 is formed on the entire surface of such a substrate in a conformal manner, and a SiOx interlayer insulating film 88 is deposited thereon and is substantially surface-planarized. A resist pattern 89 (PR) is formed on the SiOx interlayer insulating film 88 by photolithography. The opening of the resist pattern 89 is sufficiently larger than an interconnection space between the adjacent gate electrodes 83.
The SiOx interlayer insulating film 88 is then dry-etched using the resist pattern 89 as a mask in a condition capable of ensuring a sufficient selective ratio to the SiN etching stopper film 87. Here, the etching characteristic of the SiN film will be compared with that of the SiOx film. Both the films are not different so much in energy of chemical bonding of crystal lattices, and they use the basically common species. Moreover, the etching rate by F* (fluorine radical) is slightly larger in the underlying SiN film. For this reason, it has been regarded that highly selective etching of the SiOx film on the SiN film is extremely difficult. In recent years, however, so-called high density plasma sources capable of achieving an ion current density of 5 mA/cm.sup.2 or more, such as an ECR plasma, induction coupling plasma (ICP) and helicon wave plasma have been variously proposed, and the above highly selective etching of the SiOx film has been performed using such a high density plasma source. Specifically, the above dry etching is performed using a plasma of a fluorocarbon based gas and the selection ratio is ensured by depositing a fluorocarbon (FC) based polymer on the surface of the underlying layer so as to form a FC based protective film 91. The reduction in etching rate due to deposition of the FC protective film is compensated by production of a large amount of an etching species in the high density plasma.
In the case where the etching selection ratio in the above dry etching is sufficiently large, the etching of the SiOx interlayer insulating film 88 is rapidly reduced in its etching rate when reaching the SiN etching stopper film 87, so that the erosion of the offset oxide film 84 and the side wall 85 is prevented. FIG. 11 shows the state in which the above steps are completed. After that, the SiN etching stopper film 87 is selectively etched in an etching condition switched for the SiN film, to complete a contact hole 90.
However, if the dry etching for the SiOx interlayer insulating film 88 is desirably performed, it is very difficult to desirably perform the subsequent dry etching for the SiN etching stopper film 87, and in most cases, an etching residue 87r remains on the bottom surface of the contact hole 90. This is because the FC based protective film 91 deposited on the surface of the SiN etching stopper film 87 has a resistance against etching and it functions as a non-uniform etching mask. Such an insulating etching residue 87r reduces an effective contact area and causes a rise in contact resistance or a contact failure, and accordingly it must be removed before formation of an upper interconnection.
To solve such a problem, there may be considered a method of physically removing the FC based protective film 91 by increasing the ion-sputter function upon dry etching of the SiN etching stopper film 87 or removing the etching residue 87r by excessive over-etching. Such a method, however, is disadvantageous in that the offset SiOx film 84 and the side wall 85 are eroded as shown in FIG. 13, to cause a fear that the gate electrode 83 is partially exposed in the contact hole 90. When the contact hole 90 is covered with an upper interconnection 92 (Al) in such a state, the upper interconnection 92 is short-circuited with the gate electrode 83 as shown in FIG. 14.
In the related art SAC process using an SiN based film as the etching stopper film, as described above, it degrades the reliability of the process that the FC based protective film having a high resistance against etching and necessary for ensuring a high selection ratio to the SiN film cannot be sufficiently removed in the subsequent process.